An information handling system (IHS) may include a processor for processing, handling, communicating or otherwise manipulating information. Modern IHSs often include integrated circuits (ICs) that incorporate several components integrated together on a common semiconductor die. Some IHSs operates as test systems that evaluate the functionality and performance characteristics of IC designs during the development process of the IC. A typical IC development process employs early design specifications that may include stringent requirements relating to the overall speed, throughput, memory performance of the IC and other requirements. For example, a design requirement of a particular IC may demand that the IC functions without failure at a predetermined clock frequency.
With often stringent requirements on IC design performance, designers try to develop extensive test strategies early in the IC development phase. It is very common to apply these test strategies before the physical IC design hardware is complete. Designers develop computer or IC design models and test various parameters of the device in a test simulation. The more detailed or accurate the IC design model, the more accurate the testing results become. However, more detailed IC models result in longer user application software execution times during testing. Test strategies may involve extensive testing with large user application software in a simulation environment. User application software is the software that the IC design will execute in normal operation. This user application software may include large numbers of instructions that often number in the trillions. Due to the large number of instructions in these applications, it may not be feasible to run or execute a user application software program on an IC design model and still evaluate results in a timely manner. Hours of a typical user application software program execution in a real world processor may correspond to months of execution time within a simulator.
What is needed is a test strategy method and apparatus that addresses the problems faced by integrated circuit IC designers described above.